Qurbanov Afad. Müasir Azərbaycan ədəbi dili. I cild (2 cilddə)

Figure 8. Optional Horizontal Luma Low-Pass Filter Responses

Muasır Azerbaycan Edebiyatı Devri (1979- )

The Bt848 provides three mechanisms to reduce the amount of video pixel data in its output stream; down-scaling, cropping, and temporal decimation. All three can be controlled independently.

Horizontal and Vertical Scaling

The Bt848 provides independent and arbitrary horizontal and vertical down scal-ing. The maximum scaling ratio is 16:1 in both X and Y dimensions. The maxi-mum vertical scaling ratio is reduced from 16:1 when using frames to 8:1 when using fields. The different methods utilized for scaling luminance and chromi-nance are described in the following sections.

Luminance Scaling The first stage in horizontal luminance scaling is an optional pre-filter which pro-vides the capability to reduce anti-aliasing artifacts. It is generally desirable to lim-it the bandwidth of the luminance spectrum prior to performing horizontal scaling because the scaling of high-frequency components may create image artifacts in the resized image. The optional low pass filters shown in Figure 8 reduce the hor-izontal high-frequency spectrum in the luminance signal. Figure 9 and Figure 10 show the combined results of the optional low-pass filters, the luma notch filter and the 2x oversampling filter. Figure 12 shows the combined responses of the luma notch filter and the 2x oversampling filter.

The Bt848 implements horizontal scaling through poly-phase interpolation.

The Bt848 uses 32 different phases to accurately interpolate the value of a pixel.

This provides an effective pixel jitter of less than 6 ns.

In simple pixel- and line-dropping algorithms, non-integer scaling ratios intro-duce a step function in the video signal that effectively introintro-duces high-frequency spectral components. Poly-phase interpolation accurately interpolates to the cor-rect pixel and line position providing more accurate information. This results in aesthetically pleasing video as well as higher compression ratios in bandwidth lim-ited applications.

For vertical scaling, the Bt848 uses a line store to implement four different fil-tering options. The filter characteristics are shown in Figure 11. The Bt848 pro-vides up to 5-tap filtering to ensure removal of aliasing artifacts.

The number of taps in the vertical filter is set by the VTC register. The user may select 2, 3, 4 or 5 taps. The number of taps must be chosen in conjunction with the horizontal scale factor in order to ensure the needed data can fit in the internal FIFO (see the VFILT bits in the VTC register for limitations). As the scaling ratio is increased, the number of taps available for vertical scaling is increased. In addi-tion to low-pass filtering, vertical interpolaaddi-tion is also employed to minimize arti-facts when scaling to non-integer scaling ratios.

Figure 8. Optional Horizontal Luma Low-Pass Filter Responses

Figure 9. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (NTSC)

Figure 10. Combined Luma Notch, 2x Oversampling and Optional Low-Pass Filter Response (PAL/SECAM)

Figure 11. Frequency Responses for the Four Optional Vertical Luma Low-Pass Filters

Figure 12. Combined Luma Notch and 2x Oversampling Filter Response

Chrominance Scaling A 2-tap, 32-phase interpolation filter is used for horizontal scaling of chrominance.

Vertical scaling of chrominance is implemented through chrominance comb filter-ing usfilter-ing a line store, followed by simple decimation or line droppfilter-ing.

Scaling Registers The Horizontal Scaling Ratio Register (HSCALE) is programmed with the hor-izontal scaling ratio. When outputting unscaled video (in NTSC), the Bt848 will produce 910 pixels per line. This corresponds to the pixel rate at f_CLKx1 (4*Fsc).

This register is the control for scaling the video to the desired size. For example, square pixel NTSC requires 780 samples per line, while CCIR601 requires 858 samples per line. HSCALE_HI and HSCALE_LO are two 8-bit registers that, when concatenated, form the 16-bit HSCALE register.

The method below uses pixel ratios to determine the scaling ratio. The follow-ing formula should be used to determine the scalfollow-ing ratio to be entered into the 16-bit register:

For example, to scale PAL/SECAM input to square pixel QCIF, the total number of horizontal pixels desired is 236:

An alternative method for determining the HSCALE value uses the ratio of the scaled active region to the unscaled active region as shown below:

In this equation, the HACTIVE value cannot be cropped; it represents the total ac-tive region of the video line. This equation produces roughly the same result as us-ing the full line length ratio shown in the first example. However, due to truncation, the HSCALE values determined using the active pixel ratio method will be slightly different than those obtained using the total line length pixel ratio method. The val-ues in Table 5 were calculated using the full line length ratio.

NTSC: HSCALE = [ ( 910/P_desired ) – 1] * 4096 PAL/SECAM: HSCALE = [ ( 1135/P_desired ) – 1] * 4096

where: P_desired = Desired number of pixels per line of video, includ-ing active, sync and blankinclud-ing.

HSCALE = [ ( 1135/236 ) – 1 ] * 4096

NTSC: HSCALE = [ (754 / HACTIVE) – 1] * 4096 PAL/SECAM: HSCALE = [ (922 / HACTIVE) – 1] * 4096

where: HACTIVE = Desired number of pixels per line of video, not in-cluding sync or blanking.

The Vertical Scaling Ratio Register (VSCALE) is programmed with the ver-tical scaling ratio. It defines the number of verver-tical lines output by the Bt848. The following formula should be used to determine the value to be entered into this 13-bit register. The loaded value is a two’s-complement, negative value.

For example, to scale PAL/SECAM input to square pixel QCIF, the total number of vertical lines is 156:

Note that only the 13 least significant bits of the VSCALE value are used; the five LSB’s of VSCALE_HI and the 8-bit VSCALE_LO register form the 13-bit VS-CALE register. The three MSB’s of VSVS-CALE_HI are used to control other func-tions. The user must take care not to alter the values of the three most significant bits when writing a vertical scaling value. The following C-code fragment illus-trates changing the vertical scaling value:

#define BYTE unsigned char

#define WORD unsigned int

#define VSCALE_HI 0x13

#define VSCALE_LO 0x14

BYTE ReadFromBt848( BYTE regAddress );

void WriteToBt848( BYTE regAddress, BYTE regValue );

BYTE oldVscaleMSByte, newVscaleMSByte;

/* get existing VscaleMSByte value from */

/* Bt848 VSCALE_HI register */

oldVscaleMSByte = ReadFromBt848( VSCALE_HI );

/* create a new VscaleMSByte, preserving top 3 bits */

/* send the new VscaleMSByte to the VSCALE_HI reg */

WriteToBt848( VSCALE_HI, newVscaleMSByte );

/* send the new VscaleLSByte to the VSCALE_LO reg */

WriteToBt848( VSCALE_LO, (BYTE) VSCALE );

If your target machine has sufficient memory to statically store the scaling val-ues locally, the READ operation can be eliminated.

VSCALE = ( 0x10000 – < [ ( 4/1 ) –1 ] * 512 >) & 0x1FFF

Note on vertical scaling: When scaling below CIF resolution, it may be useful to use a single field as opposed to using both fields. Using a single field will ensure there are no inter-field motion artifacts on the scaled output. When performing sin-gle field scaling, the vertical scaling ratio will be twice as large as when scaling with both fields. For example, CIF scaling from one field does not require any ver-tical scaling, but when scaling from both fields, the scaling ratio is 50%. Also, the non-interlaced bit should be reset when scaling from a single field (INT=0 in the VSCALE_HI register). Table 5 lists scaling ratios for various video formats, and the register values required.

Table 5. Scaling Ratios for Popular Formats Using Frequency Values

Image Cropping Cropping enables the user to output any subsection of the video image. The AC-TIVE flag can be programmed to start and stop at any position on the video frame as shown in Figure 13. The start of the active area in the vertical direction is refer-enced to VRESET (beginning of a new field). In the horizontal direction it is ref-erenced to HRESET (beginning of a new line). The dimensions of the active video region are defined by HDELAY, HACTIVE, VDELAY, and VACTIVE. All four registers are 10-bit values. The two MSBs of each register are contained in the CROP register, while the lower eight bits are in the respective HDELAY_LO, HACTIVE_LO, VDELAY_LO and VACTIVE_LO registers. The vertical and hor-izontal delay values determine the position of the cropped image within a frame while the horizontal and vertical active values set the pixel dimensions of the cropped image as illustrated in Figure 13.

Video Scaling, Cropping, and Temporal Decimation

Figure 13. Effect of the Cropping and Active Registers

Beginning of a New Frame

Beginning of a New Line Video frame

Horizontally Active Horizontally Inactive

Cropping Registers The Horizontal Delay Register (HDELAY) is programmed with the delay be-tween the falling edge of HRESET and the rising edge of ACTIVE. The count is programmed with respect to the scaled frequency clock. Note that HDELAY should always be an even number.

The Horizontal Active Register (HACTIVE) is programmed with the actual number of active pixels per line of video. This is equivalent to the number of scaled pixels that the Bt848 should output on a line. For example, if this register contained 90, and HSCALE was programmed to downscale by 4:1, then 90 active pixels would be output. The 90 pixels would be a 4:1 scaled image of the 360 pixels (at CLKx1) starting at count HDELAY. HACTIVE is restricted in the following man-ner:

HACTIVE + HDELAY ≤ Total Number of Scaled Pixels.

For example, in the NTSC square pixel format, there is a total of 780 pixels, in-cluding blanking, sync and active regions. Therefore:

HACTIVE + HDELAY ≤ 780.

When scaled by 2:1 for CIF, the total number of active pixels is 390. Therefore:

HACTIVE +HDELAY ≤ 390.

The HDELAY register is programmed with the number of scaled pixels be-tween HRESET and the first active pixel. Because the front porch is defined as the distance between the last active pixel and the next horizontal sync, the video line can be considered in three components: HDELAY, HACTIVE and the front porch.

See Figure 14. When cropping is not implemented, the number of clocks at the 4x sample rate (the CLKx1 rate) in each of these regions is shown below:

The value for HDELAY is calculated using the following formula:

HDELAY = [(CLKx1_HDELAY / CLKx1_HACTIVE) * HACTIVE] & 0x3FE CLKx1_HDELAY and CLKx1_HACTIVE are constant values, so the equation becomes:

NTSC:HDELAY = [(135 / 754) * HACTIVE] & 0x3FE PAL/SECAM:HDELAY = [(186 / 922) * HACTIVE] & 0x3FE In this equation, the HACTIVE value cannot be cropped.

The Vertical Delay Register (VDELAY) is programmed with the delay be-tween the rising edge of VRESET and the start of active video lines. It determines how many lines to skip before initiating the ACTIVE signal. It is programmed with the number of lines to skip at the beginning of a frame.

The Vertical Active Register (VACTIVE) is programmed with the number of lines used in the vertical scaling process. The actual number of vertical lines output from the Bt848 is equal to this register times the vertical scaling ratio. If VSCALE is set to 0x1A00 (4:1) then the actual number of lines output is VACTIVE/4. If VS-CALE is set to 0x0000 (1:1) then VACTIVE contains the actual number of vertical lines output.

Note: It is important to note the difference between the implementation of the horizontal registers (HSCALE, HDELAY, and HACTIVE) and the vertical regis-ters (VSCALE, VDELAY, and VACTIVE). Horizontally, HDELAY and HAC-TIVE are programmed with respect to the scaled pixels defined by HSCALE.

Vertically, VDELAY and VACTIVE are programmed with respect to the number of lines before scaling (before VSCALE is applied).

Temporal Decimation Temporal decimation provides a solution for video synchronization during periods when full frame rate can not be supported due to bandwidth and system restric-tions.

For example, when capturing live video for storage, system limitations such as hard disk transfer rates or system bus bandwidth may limit the frame capture rate.

If these restrictions limit the frame rate to 15 frames per second, the Bt848’s time scaling operation will enable the system to capture every other frame instead of al-lowing the hard disk timing restrictions to dictate which frame to capture. This maintains an even distribution of captured frames and alleviates the “jerky” effects caused by systems that simply burst in data when the bandwidth becomes avail-able.

The Bt848 provides temporal decimation on either a field or frame basis. The temporal decimation register (TDEC) is loaded with a value from 1 to 60 (NTSC) or 1 to 50 (PAL/SECAM). This value is the number of fields or frames skipped by the chip during a sequence of 60 for NTSC or 50 for PAL/SECAM. Skipped fields and frames are considered inactive, which is indicated by the ACTIVE pin remain-ing low.

Figure 14. Regions of the Video Signal

When changing the programming in the temporal decimation register, 0x00 should be loaded first, and then the decimation value. This will ensure that the decimation counter is reset to zero. If zero is not first loaded, the decimation may start on any field or frame in the sequence of 60 (or 50 for PAL/SECAM). On power-up, this preload is not necessary because the counter is internally reset.

When decimating fields, the FLDALIGN bit in the TDEC register can be pro-grammed to choose whether the decimation starts with an odd field or an even field. If the FLDALIGN bit is set to logical zero, the first field that is dropped dur-ing the decimation process will be an odd field. Conversely, settdur-ing the FLDALIGN bit to logical one causes the even field to be dropped first in the dec-imation process.

TDEC = 0x02 Decimation is performed by frames. Two frames are skipped per 60 frames of video, assuming NTSC decoding.

Frames 1–29 are output normally, then AC-TIVE remains low for one frame. Frames 31–59 are then output followed by another frame of in-active video.

TDEC = 0x9E Decimation is performed by fields. Thirty fields are output per 60 fields of video, assuming NTSC decoding.

This value outputs every other field (every odd field) of video starting with field one in frame one.

TDEC = 0x01 Decimation is performed by frames. One frame is skipped per 50 frames of video, assuming PAL/SECAM decoding.

TDEC = 0x00 Decimation is not performed. Full frame rate video is output by the Bt848.

Qurbanov Afad. Müasir Azərbaycan ədəbi dili. I cild (2 cilddə)

Təkmilləşdirilmiş 5-ci nəşr. — Bakı: Azərbaycan Milli Elmlər Akademiyas, 2019. — 463 səh. — (Afad Qurbanovun “Seçilmiş əsərləri“). — ISBN 9789952835816.

Kitabda Azərbaycan dili, onun tarixi, forma və üslubları qısa şəkildə izah edilir. Bunlarla bərabər, Azərbaycan ədəbi dilinin fonetik sistemi, lüğət tərkibi və onlara aid linqvistik xüsusiyyətlər geniş şərh olunur. Həmçinin müasir Azərbaycan dilinin orfoepiya, yazı, qrafika və orfoqrafiya məsələləri də elmi-nəzəri əsasda aydınlaşdırılır. Əsərdən müəllim və tələbələr, aspirant və dissertantlar, mətbuat və nəşriyyat işçiləri, radio və televiziya əməkdaşları, eləcə də Azərbaycan ədəbi dilinin qayda-qanunları ilə maraqlananlar faydalana bilər. Dərslik Azərbaycan Respublikası Təhsil Nazirliyi tərəfindən təsdiq edilmişdir.

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​”Müasir Azərbaycan ədəbiyyatı antologiyası”nın müxtəlif ölkələrdə təqdimatı olacaq

Bakı. 4 noyabr. REPORT.AZ/ Nazirlər Kabineti yanında Tərcümə Mərkəzi Azərbaycan ədəbiyyatının dünya dillərinə tərcüməsi və beynəlxalq müstəvidə tanıdılması istiqamətində iş aparır. Mərkəzdən “Report”a daxil olan məlumata görə, bu fikirləri mərkəzin direktoru Afaq Məsud Yaponiyanın fövqəladə və səlahiyyətli səfiri Tsuquo Takahaşi ilə görüşü zamanı deyib. O bildirib ki, artıq bir neçə dilə tərcümə edilmiş “Müasir Azərbaycan ədəbiyyatı antologiyası”nın ayrı-ayrı ölkələrdə təqdimatı gözlənilir: “Yaponiyaya gəlincə, burda məsələ bir qədər çətindir. Bildiyiniz kimi, yapon dilinin tədrisinə Azərbaycanda bir neçə ildir başlanılıb. Bu mənada, Azərbaycan dilində yazılmış bədii əsərin orijinaldan yapon dilinə birbaşa tərcüməsi uzun bir zaman kəsiyi tələb edən məsələdir. Lakin bu işə yapon dilinə edilmiş sətri tərcümələr və köməkçi mətn kimi, əsərlərin rus, yaxud türk dilinə tərcümə olunmuş ədəbi mətnlərindən istifadə ilə başlaya bilərik. Sonrakı mərhələdə əsərlərin yapon dilində bədii tərcüməsinin alınmasına bizə yapon tərcüməçiləri, bu işə marağı olan yazıçı və şairlər kömək edə bilərlər”. Səfir isə deyib ki, Azərbaycan ədəbiyyatının Yaponiyada tanıdılması istiqamətində müəyyən işlər görülməlidir. Onun sözlərinə görə, ilk növbədə yapon dilinin tədrisi istiqamətində tərcüməçilik ixtisasının formalaşdırılması vacibdir.